Swadeshi Microprocessor Challenge UPSC

Swadeshi Microprocessor Challenge | UPSC

      HEADLINES:

Shri Ravi Shankar Prasad launches “Swadeshi Microprocessor Challenge” to realize the ambition of self-reliance and a momentous stride towards “Atmanirbhar Bharat”

      WHY IN NEWS:

Registration process begins on 18th August 2020 through MyGov portal

MINISTRY? :-Ministry of Electronics & IT
SYLLABUS COVERED: GS 3: Science and Technology : Electronics : Semiconductors

      LEARNING: 

For PRELIMS this article wants you to dive into basic electronic . Concentrate on Aim , Processors and expected outcome .

For MAINS do you think for larger computational needs we should rely on only IIT’s ? How can we enlarge the scope of Digital India ?

      CONTEXT: 

Indigenously developed microprocessors SHAKTI and VEGA have been rolled . 

SWADESHI MICROPROCESSOR CHALLENGE

TITLE

Swadeshi Microprocessor Challenge– Innovate Solutions for #Aatmanirbhar Bharat”.

AIM

  • To provide further impetus to the strong ecosystem of Start-up, innovation and research in the country.

SHAKTI and VEGA have been rolled out under the aegis of Microprocessor Development Programme of MeitY.

ORGANISERS

The challenge is made available by IIT Madras (शक्ति processors) and C-DAC (वेगा processors), powered by FPGA Boards of XILINX which is supported by CoreEL Technologies funded by MEITY.

TIMELINE

  • The Challenge spread over 10 months, kick-starts with registration process at on 18th August 2020 and culminates in June 2021.

PROCESSORS

  • IIT Madras and Center for Development of Advance Computing (CDAC) have developed two microprocessors named SHAKTI (32 bit) and VEGA (64 bit) respectively.
  • These are using Open Source Architecture under the aegis of MEITY.

SHAKTI MICROPROCESSOR

Swadeshi Microprocessor Challenge

Shakti chip board
Image Credit: IIT Madras
  • The Indian Institute of Technology (IIT) Madras has released the software development kit (SDK) for its open-source Shakti processor.
  • Shakti is based on the open-source RISC-V instruction set architecture .

The RISE group at IIT Madras started working on the Shakti project in 2016

  • The plan was to release a family of six classes of processors, each serving a different market.
  • The group promised that the reference processors will be competitive with commercial offerings in terms of area, performance and power consumption.

VEGA PROCESSOR

  • C-DAC has successfully completed the design, development and validation of a series of 32-bit /64-bit Single and Multi-core high performance processors named ‘VEGA’.

It is based on the open source RISC-V Instruction Set Architecture (ISA) with Multilevel Caches.

  • C-DAC has also integrated a wide range of in-house developed Silicon proven System and Peripheral IPs .
  • The complete software ecosystem comprising of the Board Support Packages ,IDE plug-ins and Debugger for development, testing and debugging is also available.

SCOPE OF स्वदेशी MICROPROCESSOR CHALLENGE

  • “Swadeshi Microprocessor Challenge- Innovate Solutions for #Aatmanirbhar Bharat” seeks to invite innovators, startups and students. 

This initiative is aimed at meeting India’s future requirements of strategic and industrial sectors .

  • Also it focuses has to mitigate the issues of security, licensing, technology and most crucially cutting dependency on imports.
  • The design, development & fabrication of these state-of-the-art processor variants at foundry in the country and abroad.
  • These are small yet successful step to leapfrog to ultimate goal of vibrant ecosystem of Electronic System Design & Manufacturing in the country.
  • The “Swadeshi Microprocessor Challenge” is part of the series of proactive, preemptive and graded measures taken by Ministry of Electronics and IT.
  • This will spur the technology led innovation ecosystem in the country and staying at the forefront of digital adoption.

Swadeshi Microprocessor Challenge | UPSC

ELIGIBILITY

  • The contest is open to all Indian students pursuing undergraduate, postgraduate & Doctoral degrees in Engineering discipline with Indian Colleges and Universities.

Teams of not more than 5 students and 2 faculty members.

  • Ministry of Electronics and IT offers a slew of benefits to the contestants like internship opportunities and regular technical guidance .

PRIZE

  • Opportunity for 100 Semi-finalists to win total Rs. 1.00 Crore of Award, 25 Finalists to win total Rs. 1.00 Crore of Award

Top 10 teams entering the finale, will get the seed fund of total Rs 2.30 Crore and 12 months of incubation support.

      IASbhai WINDUP: 

EXPECTED OUTCOMES

  • REWARDS AND RECOGNITION : Participants will Win lucrative prize money at various stages of the Challenge.
  • FAST TRACK FUTURE : It is platform to innovate and demonstrate capabilities.
  • VISIBILITYA high viewership platform provides you with an opportunity to showcase and promote your innovation.
  • BE MENTORED BY THE BESTOpportunity to gain mentorship and guidance under the best VLSI & Electronics System Design Experts in the country.
  • EXPAND YOUR REACHOpportunity to meet peers, domain experts and other stakeholders.
     SOURCES:THE HINDU & PIB/DAILY CURRENT AFFAIRS for UPSC CSE Prelims & Mains

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